standard cell design
英 [ˈstændəd sel dɪˈzaɪn]
美 [ˈstændərd sel dɪˈzaɪn]
网络 标准单元设计
双语例句
- Two types of C-element are designed and implemented in this standard cell design flow. The transistor sizes of these C-elements are optimized for performance.
本文提出了一种异步标准单元的设计流程，设计实现了两种兼容已有标准单元库标准的异步集成电路C单元，并对其进行了性能优化。 - ECOP: A Row-Partition Based Incremental Placement Algorithm for Standard Cell Layout Design
ECOP：一种基于单元行划分的标准单元模式增量布局算法 - The chip layout redesigns adopt 3 μ m P-well silicon gate single metal CMOS layout design rules. Logic combination circuit layout adopts standard cell design which reduces chip area on the whole.
芯片版图的再设计采用了3μm的P阱硅栅单层金属CMOS版图设计规则，对逻辑组合电路部分的版图采用了标准单元的设计，从整体上缩小了芯片的面积。 - Timing driven layout system for gate array and standard cell design& Tiger
时延驱动的门阵和标准单元布图系统&Tiger - The Placement Procedure in a Standard Cell Approach Auto Layout Design System
标准单元法自动布图设计系统中的布局过程 - Timing Simulation of Network Delay in CMOS Standard Cell Layout Design
CMOS标准单元版图线网延迟的计算机时序模拟 - Standard cell based semi-custom design flow and methodology was explored in this paper too.
本文还就指令控制部件的结构设计、综合优化以及设计验证探索了基于标准单元的高性能微处理器的半定制设计流程和方法。 - Then, multiple design methods are adopted to cut chip power consumption. After reasonable power simulation based on perfect power modeling of standard cell and memory module, these low power design methodologies are verified as effective.
在采用多种低功耗设计技术用以降低这些因素的影响之后，通过对标准单元和存储器进行功耗建模，并应用基于功耗模型的功耗仿真，验证了MP3解码芯片低功耗设计的有效性。 - The realization method of SoC is variety. Generally It is based on standard cell semi-custom design approach. In addition, it also can use full-custom design flow and FPGA design flow.
SoC集成电路有多种实现方法，通常我们采用基于标准单元半定制设计方法，除此之外，还采用全定制的设计方法，FPGA设计方法，他们各有优缺点，在不同场合有不同的应用。 - Considering the result of half-custom design based on standard cell is hard to satisfy the requests, the full-custom design method is needed.
鉴于目前基于标准单元半定制设计的寄存器文件速度难以满足设计要求，因此有必要对其进行全定制设计。 - It could be concluded from the practical experiment that the semi-custom design method based on extended standard cell library could shorten the critical path delay and improve circuit frequency effectively in mainstream technology design.
经过实验仿真和验证，主流工艺下基于可扩展标准单元的半定制电路设计方法能够有效地缩短关键路径延时，提升电路主频性能。 - The standard cell library is a foundation to ASIC Design, its quality and performance is vital to ASIC Design.
标准单元库是ASIC设计的基础，它的质量和性能对ASIC设计来说至关重要。 - The standard cell might be extended arbitrarily on design request, that is, design automation could be realized and the very method had advantageous portability for mainstream technology.
方法可根据设计需求任意扩展标准单元，能够实现设计自动化，具有良好的可移植性，适用于主流工艺。 - As the macro-cell can achieve much more complex than the standard cell features, the method can improve the design efficiency.
由于宏单元能够实现比标准单元复杂的功能，因而可提高设计效率。